The invention relates a single-comparator technique for avoiding errors caused by MOS threshold voltage hysteresis produced in the comparator during successive approximation testing of a most significant group of bit capacitors of a CDAC capacitor array, and preventing such hysteresis from producing errors in subsequent successive approximation testing of a least significant group of bit capacitors of the CDAC capacitor array.
It is well known that successive approximation analog-to-digital converters of the type including a CDAC (capacitor digital-to-analog converter) using switched capacitor arrays of binarily weighted capacitors can be economically implemented using CMOS technology. Commonly assigned Pat. Nos. 4,940,981 (Naylor et al.) and 4,947,169 (Smith et al.) are indicative of the state-of-the-art. It also is known that during successive approximation testing of the most significant bits the output voltage changes produced by the CDAC capacitor array are sufficiently large (typically as large as one or two volts) to cause a momentary shift (sometimes referred to as "hysteresis") in the MOS threshold voltage of the input differential MOSFET stage of the comparator. Once the differential input voltage to the gate electrodes of the differential MOSFET input stage returns to a balance condition (i.e., zero volts), the shifted threshold voltage of the MOSFETs will require from a few microseconds to tens of milliseconds to "relax". The lengthy duration of this MOS threshold voltage shift greatly exceeds the conversion time of the analog-to-digital converter, and consequently can produce errors in the conversion process, especially when making critical bit decisions within a few microvolts of a balanced condition at the gate electrodes of the MOSFETs of the differential input stage.
Pat. No. 5,006,853, entitled "HYSTERESIS-INSENSITIVE ANALOG-TO-DIGITAL CONVERTER SYSTEM USING A COARSE COMPARATOR AND A FINE COMPARATOR", hereinafter referred to as the Kiriaki reference, discloses a system in which a "coarse comparator" and a "fine comparator" are utilized. The coarse comparator is used to test the most significant bit capacitors of a CDAC capacitor array, and the fine comparator is used to test a group of least significant bit capacitors thereof. FIG. 1 of the present application discloses the Kiriaki et al. technique. The Kiriaki reference describes the MOS threshold voltage hysteresis that is produced in a "coarse" MOSFET comparator 36A (with capacitor input isolation switch 7A closed) during successive approximation testing of the most significant group of "bit capacitors". The Kiriaki reference solves this problem by isolating "fine comparator" 36B in FIG. 1 hereof from conductor 12 by opening switch 7B during testing of the n most significant bit capacitors of the CDAC capacitor array 13A. Since capacitor input isolation switch 7A is closed, and since the voltage changes on CDAC array output conductor 12 during testing of the m most significant bit capacitors are large enough to induce MOS threshold shifts into the input MOSFETs of coarse comparator 36A, the input MOSFETs of coarse capacitor 36A undergo an MOS threshold voltage shift, potentially causing an erroneous decision while testing the n most significant bits. However, the input MOSFETs of fine comparator 26 are isolated by open switch 7B from such voltage swings of conductor 12 until all of the n most significant bit capacitors have been tested, so the input MOSFETs of fine comparator 36B do not see the large voltage swings and consequently no MOS threshold shift is caused therein. Then, when the m least significant bit group of CDAC capacitor bits are tested, switch 7A is open and switch 7B is closed. For the m least significant bit capacitors, the voltage on conductor 12 does not swing through a large enough range to produce a shift in the MOS threshold voltage of the input MOSFETs of fine comparator 36. Errors in the conversion of the least significant bits due to MOS threshold voltage shift therefore are avoided. Conventional digital error correction techniques are used to correct any erroneous bit decisions that may have been made while testing the n most significant bits.
The technique disclosed in the Kiriaki reference requires two comparators. This results in excessive power dissipation, excessive circuit complexity and excessive consumption of semiconductor chip surface area. The resistances of the series switches 7A and 7B increase the thermal noise of the circuit. The large MOSFETs required to implement switches 7A and 7B also may result in charge injection problems. The requirement of providing two separate comparators results in substantially increased semiconductor chip area and increased power consumption over prior comparators used in successive approximation analog-to-digital converters.
There is a need for improved comparator circuitry and an improved technique in a CMOS successive approximation digital-to-analog converter to overcome the foregoing difficulties, making it more practical to produce a CMOS successive approximation digital-to-analog converter with accuracy that exceeds 11 to 12 bits.